Half Adder is a digital combinational circuit that is used for the addition of two bits and provides an output in the form of a sum bit and a carry bit. The logical functional equations that relate the outputs S and C of a half adder circuit to the input bits are given below:-

Sum(S) = A ex-OR B

Carry(C) = A.B

Thus a half adder circuit can easily be synthesized by using 1 ex-OR gate and 1 AND gate. Since a half adder circuit can only be used to add two bits, it becomes obsolete in case of multi-bit addition in practical applications.

A full adder circuit is the one that is used for addition of three bits. It is more complex than a half adder circuit. Let A,B and C be the input bits of a full adder and S and C be the output bits, then the logical equations that relates the outputs to the inputs are:-

S= A (ex-OR) B (ex-OR) C

C= AB + C (A+B)

Thus two ex-OR gates, two AND gates and two OR gates can be used for the hardware synthesis of the circuit. These full adder circuits are the ones that can be used for multi bit addition of numbers.

In addition of multiple bits, the carry output from a full adder being used for the addition of bits at ones place is fed as an input bit to the full adder being used for the addition of the bits at the next significant place and so on. The sum bits from all the full adders along with the carry bit from the full adder dealing with the most significant bits is available to the user as an output. The carry input to the full adder dealing with the least significant place should be made ‘0’ by the user.

In market, only 4 bit full adders and 8 bit full adders are available in IC form and they need to be combined for addition of higher number of bits such as 16 and 32. The biggest disadvantage of a multi-bit full adder is the large propagation delay that is encountered in the transmission of carry bits from one adder block to the other. That is the reason why these have been replaced by more sophisticated designs such a look ahead carry adder in practical computational systems.

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