What are a Parity Bit and a Parity Generator
Whenever a digital bit stream of data is transmitted from one point to another, there is always a probability of occurrence of an error in it. A ‘0’ bit can change in to a bit or vice versa due to addition of unwanted noise to the signal from the channel and the surroundings. To check these errors in a signal stream, an extra bit known as the ‘Parity bit’ is added to the bit stream that signifies whether the stream has an even or an odd number of ones. This parity bit is 1 for odd number of ones in an odd parity system and it is 1 for even number of ones in an even parity system. The following example clarifies on the concept of how a parity bit can be used for the detection of errors:-
Let in an odd parity system, a group of four bits 1101 are to be transmitted in the network. Since the number of 1 in the bit stream are 3 which is an odd number, a parity bit P=1 is added to the bit stream and then the five bits are transmitted to the destination. Now in the channel, let one of the 1 in the stream changes to a 0 and the four bits that are received at the destination terminal as a result are 1001. On checking the number of 1’s in the bit stream which is even now against the parity bit P=1 which signifies an odd number of 1 in the stream when it was first transmitted, an error is clearly detected in the received bit packet. The Parity method is only useful for a single bit error in the data stream. If errors in multiple bits occur, then a parity method becomes obsolete for the detection of errors. For such errors, more sophisticated error detection methods like Cyclic Redundancy Check, BLOCK Coding etc are used.
A ‘Parity Generator’ is a digital combinational circuit that is used to generate the parity bit for an n-bit data stream according to the number of 1’s in the stream itself. In an n-bit odd parity system, this circuit can easily be synthesized by using n-1 ex-OR gates. The parity bit can be obtained by performing the ex-OR operation between all the n-bits by using the aforementioned gates. In an even parity system, this circuit can be synthesized by simply compliment the ex-OR gates by ex-NOR gates.