What is a 2s Compliment Subtractor

Instead of designing separate subtraction logic in digital circuitry, an n-bit full adder circuit can also be used to carry out an n-bit subtraction by employing 2’s compliment subtraction arithmetic. This leads to a lot of saving in terms of digital hardware along with space and thus is widely used in computers and other digital systems.

In 2’s Compliment subtraction arithmetic, the 2’s compliment of the subtrahend is added to the normal binary form of the minuend in order to obtain the subtraction result. Thus a 2’s compliment Subtractor can easily be synthesized by using a 2’s compliment circuitry in conjunction with a Full Adder Circuitry that is also being used for implementing addition in the system.

Let us assume that a 4-bit Subtractor has to be synthesized by using a 4-bit full adder circuit that is already being employed in the system for addition purposes. In addition to the full adder, the only digital hardware that will be required is four 2-input ex-OR gates.

The first four bit number A is fed in to the adder circuit directly while each bit of the second number B is fed in to one ex-OR gate along with the addition/subtraction logic bit that is fed in to all of the four gates. The output of the four ex-OR gates is then fed in to the 4-bit full adder as its second input number. The addition/subtraction bit is also fed in to the 4 bit adder as a Carry-in bit.

Now when the addition/subtraction bit is 0, then the output bits of the ex-OR gates are same as that of the original bits and therefore the final output from the full adder provides the sum of the two numbers. When the addition/subtraction bit is 1, then the output bits of the ex-OR gates are the 1’s compliment of the original bits. Since the carry-in bit to the adder is also 1 now, therefore it adds the 2’s compliment of the second number to the first number and provides us with the subtraction result.

The subtraction output is interpreted according to the representation used for the two input four bit numbers. If unsigned representation is used and output carry bit is 0, then the four sum output bits of the adder represents a negative subtraction term in its 2’s compliment form. If the output carry bit is 1, then the four sum output bits represent a positive subtraction term in original binary form.

In case a signed representation is used for the input numbers, then the MSB of sum output bits represents the sign while the other three bits represent the magnitude of the subtraction term.  If the MSB is 1, then the term is negative and in its 2’s compliments form. If it is 0, then the term is positive and in its original binary form.

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