What is a Carry Look Ahead Adder
In multiple addition using full adder circuits, an ample amount of delay is encountered in the processing due to the propagation delay of the carry bit between successive stages. This delay can adversely affect the speed of computing systems. One way to fasten up the addition process is the use of a Carry Look Ahead Adder in place of a full adder circuit. A carry look ahead adder is based on the pre-computation of the carry bits at the same time using a CLA (Carry look ahead) logic and then using these carry bits to generate the subsequent sum bits. On closely examining the truth table for the output carry bit C(n) for the nth stage of an adder circuit, the following expression can be deduced for it:-
C (n) = A (n).B (n) + (A (n) ex-OR B (n)).C (n-1)& (1)
Where A (n) and B (n) are the input bits of the stage and C (n-1) is the carry bit from the previous stage.
Expression (1) can also be written as:-
C (n) = G (n) + P (n). C (n-1) (2)
Where G(n) = A(n).B(n) and P(n) = A(n) ex-OR B(n)
Assuming that a three bit adder circuit is to be designed, the following logical relations can be written for the various carry bits using expression (2):-
C(0) = G(0) + P(0).C(-1)
C(1)=G(1) + P(1).G(0) + P(1).P(0).C(-1)
C(2)=G(2) + P(2).G(1) + P(2).P(1).G(0) + P(2).P(1).P(0).C(-1)
For the above three expressions, a CLA logic can be synthesized by using the required gates and all the carries can be generated at the same time after three stages of gate switching. The logic can be extended for more number of bits but the generation time remains the same. The various sum bits can then be generated using the Carry bits mentioned above using the following logical functions:-
S(0) = P(0) ex-OR C(-1)
S(1) = P(1) ex-OR C(0)
S(2) = P(2) ex-OR C (1)
Thus the three sum bits and the final output carry C(2) are generated only after four stages of gate switching in a CLA logic. Though it provides extra speed but there is a trade-off in the form of extra logic circuitry required when it is compared to full adder addition circuit for the same number of bits. Also the modularity of the design in a CLA logic decreases along with an increase in its complexity as higher Carry bits are needed to be generated.
Due to the fan-in and fan-out limitations of a gate, a CLA logic can be only be designed for a certain maximum number of bits. If the bit requirement is higher, then CLA logic can be used in a cascade structure to fulfill the design requirement.