# What is a Flip-Flop

We know that a latch is a digital circuit that can store one bit of data in it. A flip-flop is nothing but a latch with clocked inputs. It provides a control mechanism that enables or disables the registration of new inputs in to a latch. This is done by performing an AND operation on all the inputs with the Clock signal C so that the inputs get registered in to the flip-flop only when the Clock signal C is high or 1.

Thus the new input signals of an S-R flip flop (input bits S and R) synthesized out of an S-R latch (input bits S* and R*) by using a clock signal C can be written as:-

S.C = S*

R.C=R*

Thus when the clock signal C is 0, the inputs to the latch are 0 irrespective of the flip-flop inputs S and R. The output of the flip flop therefore retains the previous output and continues to act as a memory element. Such a control mechanism can help a designer to make sure that an output state of a flip-flop is available for use by the subsequent circuits in the system for as long as required without having to worry about any fluctuations in the input bits.

It is a good practice in digital systems to make changes in the inputs when the clock is low and then make the clock high to let the inputs to get absorbed in to the system. If any fluctuations in the input occur during the clock period, then the outputs will change with a chance of the previous output not getting processed by the subsequent circuitry and the system becomes unreliable.

The importance of this control mechanism is so much that flip-flops are now regarded as the basic memory elements in digital systems rather than latches. The flip flops are the basic building blocks of complex systems like shift registers, binary counters etc. Some of the most popular flip-flops are:

S-R Flip Flop D Flip Flop or Data Flip Flop. It is synthesized by shorting the S-R inputs and using an inverter before R. It is the basic building block of shift registers. J-K Flip Flop. It is synthesized by performing AND operations between S and Q bit and also R and Q bit and then driving the S-R flip flop by the outputs of these AND gates. Master-Slave J-K Flip Flop. It is synthesized by using two J-K flips in a Master-slave configuration to eliminate the race around condition.

T Flip-Flop. It is synthesized by shorting the inputs of an edge triggered J-K flip flop. It is used in binary counters.

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