What is a Synchronous Counter

One of the huge drawbacks of  an asynchronous binary sequence counter is the propagation delay encountered to obtain the final count due to to the clock having to ripple through all the flip flops of the counter. Thus a better design configuration is required to get rid of this delay and this is obtained in the form of a synchronous counter.In a synchronous counter, there is no question of a propagation delay because of the reason that the clock is fed in to all of the T flip flops at the same time. A 4 bit synchronous counter can be obtained by using four edge trigerred T flip flops in the following configuration:-

The input of the first flip flop T is made ‘1’. The input of the second flip flop is connected to the output Q1 of the first flip flop. The input of the third flip flop is the signal obtained after performing AND operation between Q1 and Q2. Similarly the input of the fourth flip flop is the signal obtained after performing AND operation between Q1, Q2 and Q3. The clock inputs of all the flip flops is connected to the system clock whose count is to be kept. The output is obtained from Q1, Q2, Q3 and Q4 lines with Q4 representing the MSB and Q1 representing the LSB of the count.

Now as the input to the first flop is always 1, its output Q1 will toggle after every clock pulse. The output Q2 will toggle only when Q1 becomes 1 and the next clock pulse occurs. Similarly Q3 will toggle only when both Q2 and Q1 becomes 1. Q4 will toggle when all the other three outputs become 1.

Thus the ouput lines of the counter will follow a natural binary sequence with the maximum count obtained when all the output lines become 1. After that all the outputs will toggle to 0 at the next clock pulse.

This synchronous counter design  is better than the asynchronous one as there are no upper limits on the frequency of the clock signal or the number of bits for which this counter can be used. This is the reason why the synchronous models are preferred over the asynchronous ones in implementing state machine models. The simplicity of design for obtaining different random sequences is another advantage of using the synchronous configuration over its counterpart.

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