# What is an Array Multiplier

An array multiplier is a digital combinational circuit that is used for the multiplication of two binary numbers by employing an array of full adders and half adders. This array is used for the nearly simultaneous addition of the various product terms involved. To form the various product terms, an array of AND gates is used before the Adder array.

To clarify more on the concept, let us take the example of a 2X2 bit multiplication with A and B being the multiplicand and the multiplier respectively. Assuming A = a(1)a(0) and B= b(1)b(0), the various bits of the final product term P can be written as:-

P(0)= a(0)b(0)

P(1)=a(1)b(0) + b(1)a(0)

P(2) = a(1)b(1) + C1 where C1 is the carry generated during the addition for the P(1) term.

P(3)=C2 where C2 is the carry generated during the addition for the P(2) term.

For the above multiplication, an array of four AND gates is required to form the various product terms like a(0)b(0) etc. and then an Adder array is required to calculate the sums involving the various product terms and carry combinations mentioned in the above equations in order to get the final Product bits.

The Hardware requirement for an m x n bit array multiplier is given as:-

(m x n) AND gates (m-1).n Adders containing at least (m-2).n full adders. The rest n can be either half adders or full adders used with the input carry kept at 0.

An array multiplier is a vast improvement in speed over the traditional bit serial multipliers in which only one full adder along with a storage memory was used to carry out all the bit additions involved and also over the row serial multipliers in which product rows (also known as the partial products) were sequentially added one by one via the use of only one multi-bit adder. The tradeoff for this extra speed is the extra hardware required to lay down the adder array. But with the much decreased costs of these adders, this extra hardware has become quite affordable to a designer.

In spite of the vast improvement in speed, there is still a level of delay that is involved in an array multiplier before the final product is achieved. For an m x n bit multiplication, let Ta be the AND gate propagation delay, Tc and Ts be the carry and sum bit propagation delay of the adder respectively. Then the final Product Delay (T) is given as:-

IF Tc>Ts, then T = Ta + [(m-1) + (n-1)].Tc

If Tc<Ts, then Ta + (m-1)Tc + (n-1)Ts

Before committing hardware resources to the circuit, it is important for the designer to calculate the aforementioned delay in order to make sure that the circuit is compatible with the timing requirements of the user.

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