What is an Asynchronous Counter

An asynchronous counter is a digital sequential circuit that is used to keep a count in a natural binary sequence. A 4 bit asynchronous counter can be synthesized by using four negative edge triggered T flip-flops in the following configuration:-

The input to all the four T flip flops is connected to a logic level ‘1’. The clock signal whose count is to be maintained is connected to the first T flip flop T1. The output of this flip flop Q1 is connected to the clock input of the second flip flop T2. Similarly Q2 is connected to the clock input of the third flip flop T3 and Q3 is connected to the clock input of the fourth flip flop T4. The output lines of the counter are then Q4, Q3, Q2 and Q1 with Q4 representing the most significant bit and Q1 representing the least significant bit of the count.

Now when an input clock is fed to the first flip flop T1, it will toggle between 1 and O on the negative edge of every clock because of the fact that the input to it is always high or ‘1’. The output of the flip flop T2 will toggle only when Q1 goes from 1 to O. Similarly Q3 will toggle only when Q2 goes from 1 to 0 and Q4 will toggle only when Q3 goes from 1 to 0.

The outputs lines of these four flip flops thus give a natural binary sequence with the count incrementing by 1 with every clock pulse. When all the lines become high i.e. the maximum count has been reached, the counter resets itself to the initial zero count at the next clock pulse. If a down count is required then the complimentary outputs of the flip flops can be used.

An n bit counter can give a count from 0 to 2n-1 and this counter is also known as Mod 2n counter. It is also possible to begin and end the count at any number in the sequence by using extra digital hardware to control the clear and preset conditions of the flip flops on the occurrence of the required conditions.

As the clock signal has to ripple through all the flip flops for the final count to be achieved, this counter is also known as a ripple counter. Because of the propagation delay that is involved in transmission of the clock from one flip flop to another, there is an upper limit on both the frequency of the clock signal and the number of bits for which this configuration can be used.

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