What is an S-R Latch

In the digital domain, S-R latch is the most basic form of a memory element that is used for storing(also known as latching) of a single bit. It can easily be synthesized by using two 2-input NOR gates.

Let us now examine the working of this latch for various input combinations:-

Let the first condition be S=1 and R=0. As S=1, it will make the output Q’ of its NOR gate as 0 irrespective of the level of Q. Now as R=0 and Q’=0, the output Q will become 1. Let us now make both the inputs to the latch R and S as 0. Now as R=0 and Q’=O from the previous state, Q will continue to be 1. Similary as S=0 and Q=1, Q’ will continue to be O. Therefore the latch here continous to retain its outputs even after the inputs from the previous state are removed and is thus acting as a memory element. Let the new inputs S=0 and R=1 are now applied to the latch. As R=1, Q will automatically becomes O. As S and Q are both O, Q’ will become 1. Now let both the inputs R and S to the latch are made O. As Q is O from the previous state, it will act along with S to keep the level of Q’ as 1. Now with Q’=1 and R=O, Q will continue to be O. Therefore the previous state of the latch is retained again even after the removal of the inputs. The final case is that of R=1 and S=1. This makes both Q and Q’ as O which is an ambiguity in itself as they both are meant to be compliment of each other. Now when these inputs are removed i.e. R and S are made 0 again, either Q or Q’ will become 1 depending upon the switching times of the gate. Therefore R=1 and S=1 is an unreliable condition and is not used.

Thus the output Q gets set i.e. becomes 1 when S=1 and R=0. Similarly it gets reset i.e. becomes 0 when R=1 and S=0. That is why S bit is also known as the set bit while R bit is also known as the reset bit of the latch. A characteristic table that sumarizes the working of an S-R latch is shown below:-

Inputs

Outputs

R

S

Q

Q’

0

0

No change in Outputs from the previous stage (Acts as memory element)

0

1

1

0

1

0

0

1

1

1

Unreliable Condition (Not used)

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