What is Level and Edge Triggering in Flip-Flops

A clock signal is used in flip flops as a control mechanism to make sure that unnecessary changes in inputs don’t affect the output of the flip flop. Traditionally, the inputs were bound to the clock signal using AND gates and thus were only registered in the flip flop when the clock signal became high. This is known as level triggering.

One of the drawbacks with level triggering was that any unwanted change in the inputs while the clock was high got registered in to the flip flop and thus affected the output which caused a certain degree of unreliability in operation. Then there was also the problem of a certain ‘race around’ condition in J-K flip flops that was caused because the outputs affected the inputs throughout the period the clock pulse remained high.

A Master-Slave configuration was devised to counter the effect of these input changes during the high period of the clock pulse; therefore making sure that there was only one change in the outputs during one clock cycle. But this configuration needed twice the hardware of an ordinary flip flop and therefore resulted in twice the propagation delay. This delay meant that the speed of the system decreased to almost half of the original value and this depreciation in speed was somewhat undesirable for cutting edge technologies.

A new hardware configuration of flip flops was thus devised which only responded to the inputs when the clock signal either went from high to low or from low to high. This is known as edge triggering and can be achieved by adding a little extra hardware logic to the flip flop circuitry. But this logic is added in parallel and therefore the number of gating stages of the circuit remains the same as the original flip flop before the output is achieved. This meant that not only the problem of the unwanted input changes was solved but the original speed of the flip flop was also maintained.

If the inputs are registered when the clock goes from low to high, then it is known as positive or rising edge triggering. If they are registered when the clock goes from high to low, then it is known as negative or falling edge triggering. The usual practice is to use the edge triggering configuration in D flip-flops because of the high speed desired in data storage applications. For J-K flip flops, Master Slave configuration is the one that is commonly used as the applications like binary counters in which they are used doesn’t require that much speed.

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